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NOP Flit Payload: A Dedicated Debug Channel
Modern PCIe systems are complex, with high-speed data transfer and intricate protocols. Traditional debug methods often struggle to provide the necessary granularity and real-time visibility into link...
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Using PSS Registers with Perspec for Portable Programming Sequences
When you use Cadence’s Perspec System Verifier and the Portable Test and Stimulus Standard (PSS) to model your system, you will likely need a way to operate on the memory-mapped registers of various...
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eMMC: The Embedded Storage Powering On-Device AI
In today's world of increasingly intelligent devices, efficient and reliable storage is paramount. Embedded MultiMediaCard (eMMC) has emerged as a crucial component that acts as the internal...
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UALink: Powering the Future of AI Compute
On April 25, the UALink Consortium officially released the UALink 200G 1.0 Specification, marking an important milestone with support from key hyperscalar market players. It enables a low-latency,...
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Insights from the Verification Software Track at CadenceLIVE Silicon Valley 2025
Earlier this month, I had the opportunity to attend CadenceLIVE Silicon Valley 2025, a premier event that brings together semiconductor and systems innovators to share how they are leveraging Cadence...
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Cadence Welcomes VLAB Works
Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation (ASTC) and a renowned leader in virtual platforms. The VLAB Works team provides an ultra-high-performance...
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The Evolution of CXL.CacheMem IDE: Insights into CXL3.0 Security Feature
In continuation of our series on IDE blogs, Why IDE Security Technology for PCIe and CXL?, Verification of Integrity and Data Encryption (IDE) for PCIe Devices, and Verification of Integrity and Data...
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Training Webinar on Protium X3: Using FullVision for Debugging
Join me, Sandeep Nasa, Senior Principal Education Application Engineer, in our free technical training webinar and discover how the Cadence Protium X3 simplifies your debugging process. We'll show you...
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Celebrating LPDDR6 Specification Publication: Cadence Hosts JEDEC LPDDR Meeting
Low-power DDR SDRAM is one of the most widely used memories in the semiconductor market today. It's used in a diverse set of applications that span mobile/handheld devices, IoT, client and server,...
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MIPI MPHY 6.0: Enabling Next-Generation UFS Performance
High-speed chip-to-chip data transfer is continuously evolving to meet increasing performance demands. MIPI MPHY is a high-speed physical layer interface developed by the MIPI Alliance. This protocol...
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UEC-LLR: The Future of Loss Recovery in Ethernet for AI and HPC
As Artificial Intelligence (AI) and High-Performance Computing (HPC) systems become the backbone of modern data centers, they generate and consume a massive amount of data. Traditional Ethernet was not...
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LPDDR6: The Next-Generation LPDDR Device Standard and How It Differs from LPDDR5
Low-power DDR SDRAM has been one of the most widely used memories in the semiconductor market today where it’s used in a diverse set of applications that spans mobile/handheld devices, IoT, client and...
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Fast Emulation Requires Fast Debug! This Is How It is Done
Introduction Emulation has become a critical tool for verifying complex system-on-chip (SoC) designs in semiconductor design. However, debugging in an emulation environment presents unique challenges...
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Scalable I/O Virtualization: A Deep Dive into PCIe’s Next Gen Virtualization
The demands of modern cloud computing—massive scale, constant agility, and tight security—are pushing traditional I/O virtualization to its limits. While SR-IOV (Single Root I/O Virtualization) was a...
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Training Insight: Unlocking the Power of the Xcelium Logic Simulator
In the fast-paced world of digital design and verification, simulation tools are the backbone of robust, error-free development. Among the industry leaders, the Cadence Xcelium Logic Simulator stands...
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